The present invention relates to a bond pad structure and a method of fabricating such structure, and more in particular, to a bond pad structure with well interface adhesion and a special disposition of via plugs to prevent from peeling of top metal pad (bonding metal layer) and fracture of top dielectric layer possibly induced during subsequent probe test procedure and wire bonding process.
Bond pads provide an integrated circuit (IC) chip with location for bonding wires or other connectors. It is obvious that when the IC chip is fabricated, its yield is affected significantly by the reliability of bond pad on itself. Nevertheless, after being manufactured, a bond pad of an IC chip usually suffers from damages during subsequent probe test procedure and wire bonding process. The cause of possible damages of the bond pads induced during probe test procedure and wire bonding process will be explained as follows.
Referring to FIGS. 1A and 1B, a bond pad structure 1 of a prior art is disclosed. FIG. 1A is a top view of the bond pad structure 1. FIG. 1B is a section view showing the bond pad structure 1 of FIG. 1A along Axe2x80x94A line. In general, the bond pad structure 1 is formed over a predetermined area defined on a semiconductor substrate (not shown). In FIG. 1A, the circle patterns with dashed line represent via plugs 123 formed underneath a top metal layer 11 (bonding metal layer) of the bond pad structure 1. As shown in FIG. 1B, the bond pad structure 1 includes at least two metal layers 11 and at least one sub-structure combination layer 12 which each is formed between two corresponding metal layers 11. It is noted that the number of the metal layers of the bond pad structure depends on the practical semiconductor manufacture. For instance, a bond pad with five metal layers is usually employed in an IC chip fabricated in 0.25 xcexcm semiconductor technology. Herein, the bond pad structure 1 with five metal layers 11 and four sub-structure combination layers 12 is also taken as an example, as shown in FIG. 1B. In general, the lowest metal layer 11 of the bond pad structure 1 is formed on an insulating layer (not shown) which is previously formed on the semiconductor substrate.
As shown in FIG. 1B, each sub-structure combination layer 12 includes a dielectric layer 121 formed over the predetermined area. The dielectric layer 121 has via openings formed through itself. Each sub-structure combination layer 12 also includes a diffusion barrier layer 122 formed over the dielectric layer 121 and the sidewalls and bottom of the via openings, and a metal material filled into the via openings to form via plugs 123. It is noted that the via plugs 123 in the bond pad structure 1 of the prior art are distributed uniformly on the predetermined area.
After being manufactured, bond pads of an IC chip must be executed a CP test that is performed by piercing a probe into the top metal layer of the bond pads and then by conducting current signal into the bond pads. Referring to FIG. 2A, a top view of the bond pad structure 1 of FIG. 1A, being executed CP test via a probe 21, is illustratively shown. Due to narrow space and inherent brittlement, part of the dielectric layers between via plugs have weak resistance to external compressive force. Therefore, during the probe test of the bond pad 1, the fracture induced by compressive force of the probe 21 possibly occurs in the dielectric layers 121. Subsequently, cracks 22 initiating from the fractured dielectric layer 121 propagate. Referring to FIG. 2B, a section view of the bond pad structure 1 in FIG. 2A is shown along Bxe2x80x94B line. As shown in FIG. 2B, the dielectric layers 121 in the bond pad structure 1 have no sufficient resistance to the propagation of the cracks 22. Thus, further damages, such as delamination or even peeling of the top metal layer 11 (boding metal layer) of the bond pad structure 1, will occur.
Besides, when a wire bonding process is performed on a bond pad, the process normally entails the bonding of a gold or aluminum wire to the bond pad by fusing the bond pad and wire together via a compressive force and an ultrasonic energy. Referring to FIG. 3A, a section view of the bond pad structure 1 of FIG. 1A, which is bonded with a wire 31, is illustratively shown along Axe2x80x94A line. Unfortunately, the compressive force and ultrasonic energy always introduces high level of shear stress xcfx84 into the bond pad structure 1 to attack weak interfaces thereof, such as metal layer 11/diffusion barrier layer 122 interface. It is expected that the bond pad structure 1 with damaged interfaces will suffer from further damages resulting from tensile stress and shear stress, such as delamination 32 and peeling of the top metal layer 11 (bonding metal layer), as shown in FIG. 3B.
Obviously, the aforesaid damages decay the reliability of the bond pads and even the performance of the IC chip with the damaged bond pads. Several researches regarding the stress buffer and interface adhesion of bond pad structure have been disclosed and are listed as follows: the U.S. Pat. Nos. 5,266,522; 5,403,777; 5,923,088; and 5,942,800.
However, the foregoing and other state-of-the-art bond pad structures still indicate the need for a new bond pad structure with well adhesion and high reliability. It is also desirable that the bond pad structure thereof is capable of resisting the propagation of cracks initiating in fractured dielectric layers during a probe test, and that the bond pad structure thereof is capable of buffering shear stress induced during a wire bonding process. The present invention is directed toward satisfying the aforesaid need.
It is an objective of the invention to provide a bond pad structure and a method of fabricating such structure whereby the bond pad structure has high reliability and well adhesion between an upper metal layer and an underneath diffusion barrier layer.
It is another objective of the invention to provide a bond pad structure and a method of fabricating such structure whereby the bond pad structure is capable of resisting crack propagation in fractured dielectric layers during a probe test to further prevent from delamination and peeling of a top metal layer of the bond pad structure.
It is another objective of the invention to provide a bond pad structure and a method of fabricating such structure whereby the bond pad structure thereof is capable of buffering stress induced during a wire bonding process to prevent from delamination and peeling of a top metal layer of the bond pad structure.
According to the invention, a bond pad structure is formed over a predetermined area A defined on a semiconductor substrate. The predetermined area A is divided into a first area B surrounding the periphery of the predetermined area A, a second area C spread at a central part of the predetermined area A, at least one pair of third areas D adjacent to the first area B, and a fourth area E between the second and third area as well as between the second and first area (B, C and D). The bond pad structure includes at least two metal layers formed over the predetermined area A and at least one structure combination which each is formed over the predetermined area A and formed between two corresponding metal layers. Each structure combination includes a dielectric layer formed over the predetermined area. The dielectric layer has via openings formed over the dielectric layer and the sidewalls and bottom via openings, a metal material filled into the via openings to form via plugs, and a second diffusion barrier layer formed over the first diffusion barrier layer via plugs formed over the first diffusion barrier layer and via plugs.
According to the invention, a method of fabricating a bond pad structure is provided. The bond pad is formed over a predetermined area A defined on a semiconductor substrate. The predetermined area A is divided into a first area B surrounding the periphery of the predetermined area A, a second area C spread at a central part of the predetermined area A, at least one pair of third areas D adjacent to the first area B, and a fourth area E between the second and third area as well as between the second and first area (B, C and D). The method is first to form a lower metal layer over the predetermined area A. Afterward, the method is to form a dielectric layer over the lower metal layer. The method is then to etch partially the dielectric layer to form via openings through the dielectric layer on the first, second and third areas (B, C and D), respectively. Afterward, the method is to form a first diffusion barrier layer over the dielectric layer and the sidewalls and bottom of the via openings. The method is then to deposit a metal material overlaying the resultant structure such that the via openings are filled with the metal material to form via plugs. Afterward, the method is to perform a planarization process to expose part of the first diffusion layer and the metal material filled within the via plugs. Afterward, the method is to form a second diffusion barrier layer over the first diffusion barrier layer and via plugs. The method is then to form an upper metal layer over the second diffusion barrier layer. The method further includes a step of reiterating N times the step of forming the dielectric layer over the metal layer through the step of forming the upper metal layer over the second diffusion barrier layer. N is equal to the result that the number of the metal layers of the bond pad structure is subtracted by two.
The advantage and spirit of the invention may be understood by the following recitations together with the appended drawings.